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- Michael Attenborough
February 24, 2006, 2:49 pm
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I have a set of modules that I have developed, originally for my own needs,
to help build and compile VHDL projects with the ModelSim simulator (VHDL is
a hardware description language used for digital electronic design and
simulation, like Verilog). I'm posting here mainly for feedback on module
naming, and I'll also be posting on comp.lang.vhdl to check there is a need
for these modules, and that I'm not otherwise wasting my time.
What the module set does (general)
* Performs a minimal recompile of a VHDL project using ModelSim, recompiling
only those design units which have changed, and those which depend on them.
No need to write and maintain compilation scripts or Makefiles.
* Feeds source files through a preprocessor if wanted (preprocessors are
selected by the first line of the source file, and are implemented as
* References any compiler errors back to the correct source file and line
* Component declarations can be automatically inserted, removing the need to
cut-and-paste each time an entity is changed.
* Compiler options can be set using special commands in comments in the
What the module set does (detail)
To use the modules you need to create a "project" object, and tell it the
filenames of the source files that you want it to work with, and locations
of some working directories. To do a project build, the project object
needs to go through two stages, a "generate" stage and a "compile" stage.
The "generate" stage involves finding which of the source files have
changed, by checking modification times, and where needed passing them
through a preprocessor and then splitting the code up into individual files
for each design unit. Component declaration insertions are done as a second
pass (this is not a preprocessor function).
The "compile" stage looks at the ModelSim library data to find dependencies
between design units, and to identify the compiled data file for each design
unit, then it calls the ModelSim compiler to recompile all the out-of-date
The program design is UI-agnostic: status reports are done via callbacks,
and errors via exceptions (well, it croaks). I started writing a Tk front
end, and this was fine, but in practice I have found it more useful to just
have a perl script to update the source files (add all files from my 'src'
directory) when I need to, and for general development I just hit F7 in my
text editor (I use SciTE) and have that set up to do the "generate and
compile". I can then double-click on any error messages to jump to the
offending line in the source file.
Module structure and proposed names
Generally, I'm proposing to put reusable VHDL-language-related components
under Hardware::Vhdl (this hierarchy already exists, and contains the only
VHDL-specific module on CPAN) and the various components of my build tool
My development modules are called:
Hardware::Vhdl::Lexer - returns lexical tokens one-by-one from a VHDL
source file. This is needed by my automake tool, but may be useful for
other purposes (like a Hardware::Vhdl::Tidy module that I have in mind)
Hardware::Vhdl::Automake::Project - defines a project class; instances
of this hold information about source files, design units, working
directories and compilation status, using instances of some of the classes
Hardware::Vhdl::Automake::SourceFile - defines a class that stores
information about a source file, and methods do split it into design units,
Hardware::Vhdl::Automake::DesignUnit - defines a class that stores
information about a design unit, its compiler options and its compilation
Hardware::Vhdl::Automake::UnitName - defines a class to store and
manipulate design unit names
Hardware::Vhdl::Automake::PreProcessor - deals with preprocessing files
(calls preprocessor plugins if requested) and returning them line-by-line
Hardware::Vhdl::Automake::PreProcessor::* - preprocessor plugins. I
will include one called Cish that is like the CPP preprocessor, and it
should be possible to write plugins to call m4, Text::CPP, Text::EP3 etc.
Hardware::Vhdl::Automake::CompileTool - base class for compiler plugins
Hardware::Vhdl::Automake::Compiler::ModelSim - a compiler plugin for
All of these use an OO API. All the classes do provide methods as well as
The modules currently only support the ModelSim simulator, because that is
the one that I have, but I've tried to structure things so that one can plug
in modules to support other compilers (or possibly synthesis tools).
The use of Verilog source files is not currently supported: it's mainly the
"generate" stage that would need to be added.
So, any comments, particularly regarding the module names? For example,
should I use something other than Hardware::Vhdl, because the tool may
support Verilog too at some point in the future?
 I ended up writing this because Text::CPP doesn't work on Win32, and
Text::EP3 has some important omissions. If it later seems worthwhile to
create Text::CishPP (or whatever I call it) as a generic preprocessor then
Hardware::Vhdl::Automake::PreProcessor::Cish will become just a plugin
interface to it.