Wrong CPU Type During POST

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Anyone know where the information comes from for identifying the CPU during
POST?  I have a Celeron 1.3GHz Tualatin that's recognized as a P-III Xeon in
a PCCHips M748LMRT.  Stepping (CPUID) is 06B1 and I've loaded the microcode
permanently into the BIOS. Apparently it's not all from the microcode.  A
Celeron 1.4GHz Tualatin, same stepping, is detected correctly.   Is
additional information obtained or derived in another BIOS module?  Using a
HEX editor I cannot find Xeon anywhere but many modules are compressed so
I'm not surprised.

Re: Wrong CPU Type During POST

mdp wrote:
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I don't have a clue for your problem but if you Google for "CPUID 06B1"
you will find that you are not alone in experiencing it. BTW, does the
problem actually stop the system from working correctly? If not I
wouldn't sweat it too much.

John McGaw
[Knoxville, TN, USA]

Re: Wrong CPU Type During POST

mdp wrote:
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Correction.  06B1 steppings show up as Pentium III Xeons.  Same results on
1.0, 1.2, and 1.3GHz cpus.  I have a 1.4GHz CPU with 06B4 stepping that
shows correctly as a Celeron CPU.  So perhaps it is in the microcode.  Also
learned Intel's microcode is encrypted so I can't search for something as
simple as Xeon within it.

Re: Wrong CPU Type During POST

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Microcode doesn't work that way. The purpose of microcode, is
to patch the operation of the CPU. The behavior of the hardware
can be modified after the fact, by Intel and their microcode
patches. All processors have errata, or design errors, that
are spotted after the hardware has shipped. Many of the error
conditions are theoretical, and cannot or will not happen on
systems that are running Windows, or using any of the popular
C compilers. Think of Microcode as being like Firmware
for your router - loading new code makes it work better
than with the old code.

The format of microcode is not documented, to prevent hackers
from creating things like microcode viruses. Imagine if a
hacker called the BIOS hook that updates the microcode cache,
with a microcode patch that caused the CPU to compute incorrectly.
Thus, expect microcode to have some level of protections applied
to it. It is only reasonable.

The header of the microcode is in clear text, and you can
see which processor family it applies to. A checksum on
the microcode helps prevent (purposeful or otherwise)

The BIOS recognizes pieces of hardware, and sets up resources
for them. On a processor, the amount of L1 and L2 cache might
be important. Perhaps the BIOS enables the cache, before handoff
to the boot code.

The BIOS also keeps a record of the hardware, in a section
of the flash chip called the DMI/ESCD. DMI is used by IT
personnel, to tell whether a user removed DIMMs from the
motherboard, or tampered with the machine. ESCD is a caching
mechanism that helps the BIOS keep track of whether there
have been any hardware changes or not. For example, if
the CPU has not changed since the last POST sequence, there
is hardly any reason to reload the microcode cache in the
flash chip. (A flash chip not only contains cpucode.exe,
but it also has a 2KB cache area, to hold the most recent
successfully loaded microcode patch.) DMI and ESCD
are writable segments of the flash chip, and the BIOS
may display "Updating NVRAM' or something similar, when
writing out new info.

http://en.wikipedia.org/wiki/Desktop_Management_Interface (DMI)

Personally, I don't see the purpose of making the BIOS
quite so "smart" - it should just do the minimum, like
read enough code off the disk, so the computer can boot.
But I guess all this BIOS functionality, has paid
the salary of generations of staff at AMI and Award,
so it is not all bad :-)

CPU recognition code is documented on the Intel web site.
Whether the BIOS adheres to the methods or algorithms, is
any ones guess. Certainly you cannot expect old code
to be tested against (at the time) non-existent processors,
so you are bound to see things like Tualatins identified
incorrectly on an older motherboard. The "CPUID" instruction
is one ingredient of the recognition process - the
06B1 is at least part of what is returned by CPUID.
The BIOS has to parse that value, and figure out what
it has got, using info like that. Every new processor
type, means more code added to the flowchart of the
recognition process.

I know there is an appropriate part of the Intel site,
that gives examples of how to write code for
recognition. I cannot find that section right now.
At least some of the info will be contained in the Intel
Architecture Manuals, available here.


Here is a code snippet. The CPUID actually returns
the word "Genuine Intel" in some of the registers, but
due to byte swaps, it is hard to see that manifest
constant in the following code.


You can decompress BIOS modules. For AMI, the mmtool.exe
full mode, offers to extract and decompress BIOS modules.
Then you can look for text strings if you like. For
Award, tools like the CTMC package will get you started
in the right direction. The AWDsplit program, breaks
an Award BIOS into modular files. The LHA decompression
program (ancient) will remove the compression, giving
the original module. Note that AWDsplit does not work
properly on Award BIOS any more - not all the modules get
extracted. I take the BIOS files apart by hand now, as I
know what the LHA header format looks like. (You cannot
miss it, if you look with a hex editor.) Then passing
the results to LHA or other general purpose decompression
programs, will return the original module.


Re: Wrong CPU Type During POST

Paul wrote:
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Very informative post.  Thanks.  I am familiar with many of the tools you
mentioned and I too use a hex editor on the BIOS and its modules.  I figured
out the header in the microcode files has every 4 bytes (2 words) rearranged
in a fixed way and wrote a script so that it appears as 'clear text' when
viewing.  I will continue to search on how the CPU name is determined
although I do realise it's purely cosmetic, the CPU works fine in the
computer despite being labeled as a Xeon.  But I do enjoy the hobby.  Thanks
again.  I will use your links to study further.

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