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- 32 Channels ADC Prallel port logger
December 10, 2010, 11:40 am
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i've build a little ADC 16 channel parallel port logger with a CD4067
MPX and a MAX187 ADC.
Now i woul like to control 32 Channel with 2 CD4067 MPX and the same
MAX 187 ADC.
What can i add to the circuit for contrl via parallel port the 2 MPX
sequencialy? Is there a site for some idea?
Thanks a lot
Re: 32 Channels ADC Prallel port logger
How many bits total does your parallel port scheme deliver ?
Do you have five bits to work with (to select one of thirty two ports),
instead of the current four bits you're using to select an input port ?
If so, you have a couple options. This first one, follows the
two CD4067, with a two input analog mux (if you can find one).
You could even use a CD4067 for the third one if you want.
This scheme degrades the "thru-resistance", meaning the settling
time to LSB could be longer on the ADC.
CD4067 --- 2 input
CD4067 --- mux
MSB of 5 bit value
The second option, uses the inhibit pin (INH) on the analog muxes.
MSB of 5 bit value -------+----- inverter -------> INH_on_CD4067_#1
(Wire the outputs of the two CD4067 together, and using the
complementary INH functions, only one CD4067 "drives the bus".)
That means you need a hex inverter pack added to your design, of
which only one of six inverters will be used.
You want to analyze the timing of the INH inhibit function, to check
for overlap between devices. It's CMOS after all, so could be quite
sloppy and stupid. If there was a need to prevent overlap, then a
more complex scheme would be needed to control the inhibit signals.
(The old CMOS may current limit to about 10mA or so, in the event
of a short circuit, unlike some TTL where the current can be ten or
more times that value. Even if they overlap, the noise pumped into
the rails might not be a big deal. Your choice, of trading simplicity
versus best performance.
That is one of the advantages of the cascaded, three mux circuit.
No worries about overlap on INH. But then the thru-resistance
is degraded a tiny bit, and that could be important. You have
to account for the RC effect of Rthru*Cin, settled to the LSB
voltage level equivalent.
By using the INH function on the CD4067, you preserve the current
thru-resistance performance, since the devices are not
When using the INH function, there is a propagation time from
INH, until the output is fully driving. You need to account for
that time, when figuring out when the analog signal will be valid
and settled. (This is probably not an issue, if you're taking
one sample per second per channel It would only be an issue if
the design was running flat out at Fmax.) I'm not going to
spoil the fun, by looking at the MAX187 datasheet, but if it
had a sample and hold, you might want to stage when it takes
a sample, away from any switching activity.
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