Two pci masters connected via pci bridge

Do you have a question? Post it now! No Registration Necessary.  Now with pictures!

Threaded View
I have a question about pci bridge.
-TMS320C6416 DSP  has a HPI/PCI bus .I want to  connect two DSPs   via
pci on a board which has no pci host  ,also there isn't another board
which can serve as a pci host and access the DSPs through a pci bridge.
May I use a  pci bridge for local connection of two DSPs without
connecting the host side of pci bridge anywhere (configuring pci bridge
 by eeprom)?

yekta ayduk

Re: Two pci masters connected via pci bridge

Quoted text here. Click to load it

             / /   \ \
  REQ/Grant / /     \ \ REQ/Grant signals
           / /       \ \
      PCI_Dev1        PCI_Dev2
           |               |
       +---+---------------+---+ A/D 32 bit bus

Example of an arbiter. Here, this is a very small IP core.

A copy of the PCI standard may contain a description of
the PCI bus arbitration operation and options. I believe
you can have peer level bus operation, as pictured above,
as long as the control signals on the bus, have the
appropriate pullup/pulldown resistors.

I don't see a reason for a PCI bridge chip, unless it is
the cheapest way to acquire the arbiter function.

I would say, you should purchase a copy of the PCI bus
spec. Or download one :-) For example, the second link
returned here, will give you a 322 page document. It is
a 3.8MB download.

This motherboard reference schematic, may help answer
some of your questions about the PCI bus. PDF page 49
shows some PCI bus termination resistors, and when no
device is driving the bus, something must be present
to keep the control signals deasserted. (Maybe a device
"parking" on the bus will do that too. Dunno.)

        +-----------------+        To be master, a device must
        |                 |        request the bus and be granted
        |                 v        control of the bus. The master
     PCI_Dev1         PCI_Dev2     (bus master) can then do
     (Master)          (Target)    transactions to the other card
                                   as its target. Once a master
        +-----------------+        nas completed a transaction, if
        |                 |        the other device wants to become
        v                 |        master, it can request the bus too.
     PCI_Dev1         PCI_Dev2     This is a form of peer to peer
     (Target)          (Master)    communication. Each target needs
                                   a unique bus decode, done with a
                                   resistor and IDSEL (PDF page 57
                                   of the PCI bus standard).

Perhaps your TI FAE can help you with the details ?

This document has a little info about the PCI
interface on that processor family.

This is how some other people connected their processors...

Just a guess,

Re: Two pci masters connected via pci bridge

Thanks a lot Paul ,I will consider your suggestions.

Yekta Ayduk

Re: Two pci masters connected via pci bridge

Quoted text here. Click to load it

Talk to your TI FAE, as that person knows the product
better than I do. There might be all sorts of reasons
not to use that method for hooking processors together.


Site Timeline