Crystal Mark memory benchmark puzzle

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I got this program and tried it out on all the PCs that I
have, right back to an ancient AT mainboard with K6-3.
Now what I noticed was the cache bandwidth on this oldie
was very poor, about same as memory write. This mainboard
has a cache chip, which becomes L3 as the K6-3 has L2.
So I think Crystal Mark is testing not the L1 but the
outermost cache, which in this case is running at FSB
hence pretty sluggish compared to internal cache.
Is this so?



Re: Crystal Mark memory benchmark puzzle



Anne Onime wrote:
Quoted text here. Click to load it

There are some benchmarking utilities, that draw a curve of
bandwidth versus test transfer size. The inflection points
in the curve, tell you the size of the various caches. You can
use a tool that runs this kind of curve, and look to see
how many levels of cache are present.

http://www.techimo.com/images/img2/hornetxp/cache.png

There were a few motherboards, back in that era, that
shipped with "empty" or "duff" cache on the motherboard.
Someone actually had the nerve to solder chips on the
motherboard, with no silicon die inside them. The result
would be, a missing level of caching.

*******

This is another one of the cache benchmarking utilities.

RightMark Memory Analyzer v3.8 (available in RAR archive or as EXE)

http://cpu.rightmark.org/download.shtml

http://cpu.rightmark.org/download/rmma38bin.rar

It gives pretty nice looking graphs. The processors here here
have two levels of cache. The fun part of the tool, is
getting the graph as a .bmp later. You use the "results"
tab, it delivers tabular data on the screen, but there is a
button to click to save as .bmp . And then you can have your
very own graph like this.

http://www.ixbt.com/cpu/rmma/p3/p3m_mmx_bw.gif

    Paul

Re: Crystal Mark memory benchmark puzzle




Quoted text here. Click to load it

Another thing is that many of those K6 mainboards did not cache all
the RAM. Typically they could take 768 MB but only cache 256 MB.
So if the benchmark programme used higher memory addresses, the
L3 cache is on holidays.


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